1. Field of the Invention
The present invention relates to a system for pipeline processing for executing a plurality of series of processings in parallel and an information processing apparatus to which this is applied, more particularly relates to a pipeline processing system of an information processing circuit employed in an optical disc device or other information recording/reproducing apparatus and decoding and encoding recording information using a memory (decoder/encoder circuit) and an information processing apparatus using the same.
2. Description of the Related Art
A decoder/encoder circuit employed in a DVD or other optical disc device performs decoder pipeline processing and encoder pipeline processing using a single buffer memory.
Below, the decoder pipeline processing and the encoder pipeline processing in a decoder/encoder circuit employed in a DVD optical disc device will be explained with reference to the drawings.
First, the decoder pipeline processing will be explained in relation to FIG. 1 and FIG. 2. FIG. 1 is a block diagram of an example of the configuration of a general decoder circuit; and FIG. 2 is a view of a state of access of decoder pipeline processing to a memory buffer in the circuit of FIG. 1. In these figures, WR indicates a write operation, and RD indicates a read operation. This decoder circuit 10 has an eight-to-fourteen modulation (EFM)+ demodulation circuit 11, an error correction code (ECC) circuit 12, an error detection code (EDC) circuit 13, a host interface circuit (HOST I/F) 14, a tracking buffer (TRCBF) 15 comprised of a dynamic random access memory (DRAM) etc., and a bus 16.
A data train sequences (RF signal) read out from an optical disc through an optical pick-up and obtained as a result of predetermined computation at an RF amplifier is subjected to binary clock extraction and supplied as a digital binary data (RF data) to the EFM demodulation circuit 11. In the EFM demodulation circuit 11, RF data (BLK1) is subjected to EFM demodulation and written into the tracking buffer 15 (EFM-WR). Next, the data stored in the tracking buffer 15 is subjected to error correction processing in the ECC circuit 12, then subjected to EDC check processing and descrambling at the EDC circuit 13. The memory access of the error correction processing is accompanied by a read operation of an inner-code parity (PI) code (PI-RD), error correction processing in accordance with the error correction result of the PI code, a read operation of an outer-code parity (PO) code (PO-RD), and error correction processing in accordance with the error correction result of the PO code. According to need, the PI correction and the PO correction are repeated. Further, the EDC data read processing and the EDC data write processing are carried out for the same tracking buffer 15. Further, according to the transfer request from a host apparatus, the data after the EDC data write processing is transferred via the host interface circuit 14 to the host apparatus. The above processings are performed by pipeline processing of the data blocks BLK1, BLK2, and BLK3 in parallel in the format shown in FIG. 2.
Next, the encoder pipeline processing will be explained in relation to FIG. 3 and FIG. 4. FIG. 3 is a block diagram of an example of the configuration of a general encoder circuit; and FIG. 4 is a view of the state of access of the encoder pipeline processing with respect to the memory buffer in the circuit of FIG. 3. In these figures, WR indicates a write operation, and RD indicates a read operation. This encoder circuit 20 has an EFM modulation circuit 21, an ECC circuit 22, an EDC circuit 23, a host interface circuit (HOST I/F) 24, a tracking buffer (TRCBF) 25 comprised of a DRAM etc., and a bus 26.
When user data transferred from the host apparatus is input to the host interface circuit 24, it is written into the tracking buffer 25 (HOST-WR). When the write operation of the user data is ended, the encoding starts. The user data is read out (EDC-RD) from the tracking buffer 25 by the EDC circuit 23, the scrambling, the EDC parity generation, the ID generation, various types of field information generation, etc. are carried out, and the scrambled user data, EDC parity, ID, and various types of field information are written into the tracking buffer 25 (EDC-WR). The ECC parity is added to the data stored in the tracking buffer 25 at the ECC circuit 22. The memory access of this encoding is accompanied by a read operation of the PI code (PI-RD), the parity portion rewrite processing of the PI code, the read operation of the PO code (PO-RD), and the parity portion rewrite processing of the PO code. Then, the EFM modulation circuit 21 performs the read operation with respect to the data stored in the tracking buffer 25 (EFM-RD) and the EFM modulation with respect to the read out data. The EFM+ modulation data is output as a binary signal, then the processing for writing data into the disc is carried out. The above processings are performed by pipeline processing of the data blocks BLK1, BLK2, and BLK3 in parallel in the format shown in FIG. 4.
Summarizing the problems to be solved by the invention, the above decoder circuit 10 and the encoder circuit 20 performed the pipeline processing used single buffer memories (tracking buffer 15, 25). As a result, as shown in FIG. 2 and FIG. 4, accesses of the pipeline processings were carried out with respect to single buffer memories, so the buffer memories were frequently accessed. Due to this, the memory access became a bottleneck, so it was hard to realize high speed reproduction.
Further, in the above decoder circuit 10 and the encoder circuit 20, the tracking buffers 15 and 25 serving as the buffer memories were usually realized by DRAMs, so the bus between the buffer memory and the circuit were configured outside the LSI. Due to this, in the above decoder circuit 10 and encoder circuit 20, this became a cause of a large power consumption.